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學術講座

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2020年1月6日學術報告(林嘉文 教授,臺灣清華大學)
2020年01月02日16時 人評論

報告題目When Deep Learning Meets IC Fabrication: A Data-Driven Prediction Approach

報告時間202016(周一)上午10:00

報告地點:計算機學院B404會議室

報告人林嘉文

報告人單位:臺灣清華大學

報告人簡介

Prof. Chia-Wen Lin received his PhD degree in Electrical Engineering from National Tsing Hua University (NTHU), Hsinchu, Taiwan in 2000. He is currently a Professor with the Department of Electrical Engineering, NTHU, Taiwan. He also serves as Deputy Director of the AI Research Center of NTHU, and Director of Multimedia Technology Research Center of the EECS College, NTHU. His research interests include image/video processing, computer vision, and video networking.

Dr. Lin is an IEEE Fellow. He is a Distinguished Lecturer of IEEE Circuits and Systems Society (CASS) during 2018-2019. He is President of Chinese Image Processing and Pattern Recognition Association, Taiwan (term: 2019-2020), and will become the Steering Committee Chair of IEEE International Conference on Multimedia & Expo (ICME). He has served as Associate Editor of IEEE Transactions on Image Processing, IEEE Transactions on Multimedia, IEEE Transactions on Circuits and Systems for Video Technology, and IEEE Multimedia. He served as a Steering Committee member of the IEEE Transactions on Multimedia during 2013-2015. He was Chair of the Multimedia Systems and Applications Technical Committee of the IEEE CASS. He has served as TPC Chair of IEEE ICME in 2010 and IEEE ICIP in 2019, and the Conference Chair of IEEE VCIP in 2018. His papers won the Best Paper Award of IEEE VCIP 2015, and the Young Investigator Award of VCIP 2005.

報告摘要

Traditionally, after ID circuit design and layout, it takes months to fabricate an IC wafer, involving a multiple-step sequence of photolithographic and chemical processing, which can significantly deform the layout patterns and is too complex to model mathematically. Usually we cannot identify defects (e.g., broken wires) of metal wires due to deformations of layout patterns caused by IC fabrication until capturing the scanning electron microscope (SEM) images of fabricated IC wafers, making the circuit design and verification very costly and time-consuming. To address the above problem, there two essential concerns in terms of IC design for manufacturability: (1) How to predict the manufactured IC circuitry from an IC layout so as to assess the layout quality accordingly in a pre-simulation process, and (2) How to automatically modify IC layout patterns so that the manufactured IC circuitry can match the desired patterns as possible. In this talk, we will show how deep-learning-based image prediction can assist IC design for manufacturability. To this end, we formulate the lithography and etching processes of metal layers as a set of nonlinear warping functions between a patch of IC layout pattern and its corresponding SEM image, and models the set of warping functions using a CNN-based LithoNet parametrized with IC fabrication parameters. Based on LithoNet, we also propose a CNN-based OPCNet that can automatically modify an IC layout pattern so that its fabricated IC circuitry well match the desired layout pattern, the so-called Optical Proximity Correction (OPC) process.

邀請人:胡瑞敏 教授


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